Furthermore, an active matrix-type image display apparatus such as a LCD (liquid crystal display) and an organic EL (Electro Luminescence) display has been widely used in view of display performance, energy saving or the like. In particular, it has come to almost constitute the mainstream as displays of cellular phones, PDAs (Personal Digital Assistant) personal computers, laptop computers, TVs and the like. Generally, a TFT (field-effect type thin film transistor) substrate is used in these displays.
For example, a liquid crystal display has a configuration in which a display material such as liquid crystal is filled between a TFT substrate and an opposing substrate, and a voltage is selectively applied to this display material for each pixel. Here, a TFT substrate means a substrate in which a TFT using a semiconductor thin film (also referred to as a semiconductor film) such as an amorphous silicon thin film or a polycrystalline silicon thin film is arranged. The above-mentioned image display apparatus is driven by the active matrix circuit of a TFT. Since a TFT is arranged in the shape of an array, a TFT substrate is also referred to as a “TFT array substrate”.
<Conventional Method for Producing TFT Substrate>
As the method for producing a TFT substrate, a 5-mask process using five masks, a 4-mask process in which the number of masks is decreased to four by half-tone exposure technology, and other processes are known.
In such a method for producing a TFT substrate, the production process tends to include many steps since five or four masks are used. For example, it is known that the 4-mask process requires 35 steps and the 5-mask process requires steps exceeding 40. So many production steps may decrease the production yield. In addition, many steps may make the production process complicated and also may increase the production cost.
(Method for Production Using Five Masks)
FIG. 41 is schematic views for explaining the conventional method for producing a TFT substrate, in which (a) is a cross-sectional view showing the state in which a gate electrode is formed, (b) is a cross-sectional view showing the state in which an etch stopper is formed, (c) is a cross-sectional view showing the state in which a source electrode and a drain electrode are formed, (d) is a cross-sectional view showing the state in which an interlayer insulating film is formed, and (e) is a cross-sectional view showing the state in which a transparent electrode is formed.
In FIG. 41(a), a gate electrode 212 is formed on a glass substrate 210 by using a first mask (not shown). That is, first, a metal (such as aluminum (Al), for example) is deposited on the glass substrate 210 by sputtering. Then, a resist is formed by a photolithographic method by using a first mask. Subsequently, the gate electrode 212 is formed into a predetermined shape by etching, and the resist is subjected to an ashing process.
Next, as shown in FIG. 41(b), on the glass substrate 210 and the gate electrode 212, a gate-insulating film 213 as an SiN film (silicon nitride film) and an α-Si:H(i) film 214 are stacked in this order. Subsequently, an SiN film (silicon nitride film) as a channel protective layer is deposited. Then, a resist is formed by a photolithographic method using a second mask (not shown). Then, the SiN film is patterned into a predetermined shape by a dry etching method using a CHF gas, an etch stopper 215 is formed, and the resist is subjected to an ashing process.
Next, as shown in FIG. 41(c), an α-Si:H(n) film 216 is deposited on the α-Si:H (i) film 214 and the etch stopper 215. Then, a Cr (chromium)/Al double-layer film is deposited thereon by vapor vacuum deposition or sputtering. Subsequently, a resist is formed by photolithographic method using a third mask (not shown). Then, the Cr/Al double-layer film is patterned by an etching method, whereby a source electrode 217a and a drain electrode 217b are formed in a predetermined shape. In this case, Al is patterned by a photo-etching method using H3PO4—CH3COOH—HNO3 and Cr is patterned by a photo-etching method using an aqueous solution of diammonium cerium nitrate. Subsequently, the α-Si:H films (216 and 214) are patterned by a dry etching method using a CHF gas and a wet etching method using an aqueous hydrazine solution (NH2NH2.H2O), whereby the α-Si:H (n) film 216 and the α-Si:H (i) film 214 are formed in predetermined shapes, and the resist is subjected to an ashing process.
Next, as shown in FIG. 41(d), before forming a transparent electrode 219, an interlayer insulating film 218 is deposited on the gate insulating electrode 213, the etch stopper 215, the source electrode 217a and the drain electrode 217b. Subsequently, a resist is formed by photolithographic method using a fourth mask (not shown). Then, the interlayer insulating film 218 is patterned by an etching method, an opening 218a for electrically connecting the transparent electrode 219 with the source electrode 217a is formed, and the resist is subjected to an ashing process.
Next, as shown in FIG. 41(e), on the interlayer insulating film 218 in a region where patterns of the source electrode 217a and the drain electrode 217b are formed, an amorphous transparent conductive film composed mainly of indium oxide and zinc oxide is deposited by sputtering. Subsequently, a resist is formed by photolithographic method using a fifth mask (not shown). Then, the amorphous transparent conductive film is patterned by a photo-etching method using an 4 wt % aqueous solution of oxalic acid as an etchant. Then, the amorphous transparent conductive film is formed in such a shape that the film electrically connects the source electrode 217a and the resist is subjected to an ashing process, whereby the transparent electrode 219 is formed.
As mentioned above, five masks are required in this conventional method for producing a TFT substrate.
(Method for Production Using Three Masks)
To improve the above-mentioned conventional technology, various technologies to produce a TFT substrate by a method in which production steps are furthermore reduced by decreasing the number of masks (from five to three, for example) have been proposed. For example, the following patent documents 1 to 7 describe a method of producing a TFT substrate using three masks.
In addition, the patent documents 8 to 14 technologies using as a semiconductor layer an amorphous oxide containing any of In, Zn and Sn.
Patent Document 1: JP-A-2004-317685
Patent Document 2: JP-A-2004-319655
Patent Document 3: JP-A-2005-017669
Patent Document 4: JP-A-2005-019664
Patent Document 5: JP-A-2005-049667
Patent Document 6: JP-A-2005-106881
Patent Document 7: JP-A-2005-108912
Patent Document 8: JP-A-2006-165527
Patent Document 9: JP-A-2006-165528
Patent Document 10: JP-A-2006-165529
Patent Document 11: JP-A-2006-165530
Patent Document 12: JP-A-2006-165531
Patent Document 13: JP-A-2006-165532
Patent Document 14: JP-A-2006-173580